1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor devices and semiconductor systems including the same.
2. Related Art
In general, a semiconductor memory device such as a dynamic random access memory (DRAM) device includes a plurality of memory cells. Each of the DRAM cells can be configured to include a single cell transistor and a single cell capacitor. The plurality of DRAM cells may be disposed at respective ones of intersections of a plurality of word lines and a plurality of bit lines. When the DRAM device operates in a read mode, one of the word lines may be selectively enabled to transfer electric charges stored in the cell capacitors of the DRAM cells connected to the selected word line onto the bit lines, and signals corresponding to the electric charges on the bit lines may be amplified by sense amplifiers connected to the bit lines. The bit lines may be pre-charged before the selected word line is enabled. The sense amplifiers may be driven by a power supply voltage. The power supply voltage may be higher than an internal voltage to obtain a fast sensing speed and a correct amplification operation thereof. This may be referred to as an over driving operation.